1. Field of the Invention
The Present Invention relates to computer technology. More particularly, the Present Invention is related a compiling method for optimizing binary code.
2. Description of Related Art
A binary code often includes save instructions and restore instructions to registers. Examples of such instructions include STM (store multiple) and LM (load multiple), which are assembler mnemonics of the z/Architecture of IBM (registered trademark). In the binary code, a large number of memory accesses are generated to store registers on a stack and to restore the registers. For this reason, to improve the performance of the computer resources, the memory accesses are replaced with register accesses to increase processing speed.
A method for renaming stack references in a computer processing system is described in U.S. Pat. No. 7,085,914 (the fourth column, lines 17 to 20). U.S. Pat. No. 7,085,914 includes the steps of detecting stack references that use architecturally defined stack access methods, and replacing the stack references with references to processor-internal registers (the fourth column, lines 21 to 27). U.S. Pat. No. 7,085,914 further includes the step of synchronizing an architected state between the processor-internal registers and a main memory of the computer processing system (the fourth column, lines 28 to 31). The method described in U.S. Pat. No. 7,085,914, however, is a new hardware mechanism to be incorporated in a computer system and is to modify processing that is performed during the execution of an instruction.
JACOBS, JOSHUA. “Improving Memory Performance through Runtime Optimization.” ME thesis. Massachusetts Institute of Technology, Cambridge, Mass., 2002. Print. describes a redundant load removal (RLR) optimization analysis (pages 23 to 28, Chapter 4 “Redundant load removal on traces”). In JACOBS, however, no optimization (removal or the like) for store instructions is performed.